The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device that can stabilize a process for forming a vertical transistor, thereby improving the characteristics and the reliability of a semiconductor device, and a method for manufacturing the same.
As the integration level of a semiconductor device increases, the area that is occupied by each unit cell decreases when viewed from above. Corresponding to the need to decrease in the area of the unit cell, various alternate methods for forming transistors, bit lines and capacitors within these diminished areas have been researched. In one approach, a semiconductor device having the structure of a transistor, hereinafter referred to as a “vertical transistor”, has been proposed. The vertical transistor has a source area and a drain area positioned up and down in an active region that defines a vertical channel in a semiconductor substrate.
Hereafter, a conventional method for manufacturing a semiconductor device having a vertical transistor will be briefly described.
After sequentially forming an oxide layer and a nitride layer on a semiconductor substrate, the nitride layer and the oxide layer are selectively etched to expose portions of the semiconductor substrate. Then, by using anisotropically etching and using the etched nitride layer as an etch mask barrier, the exposed portions of the semiconductor substrate are etched at a predetermined depth to define first grooves in the semiconductor substrate.
After forming spacers on the sidewalls of the nitride layer and using the etched nitride layer and the spacers as etch mask barriers, the oxide layer and the first grooves are isotropically etched at the bottoms of the first grooves to define second grooves under the first grooves. As a result, the second grooves have a larger width than the first grooves. As a consequence, (hereinafter referred to as a “pillar structures”) are formed which are delimited by the first and second grooves and have neck parts on lower portions thereof due to the formation of the second grooves.
Gates are subsequently formed to surround the lower portions of the pillar structures which define the second grooves. Thereafter source areas and drain areas are respectively formed in the upper and lower portions of the pillar structures with respect to the gates. As a result vertical transistors are formed that have channels aligned vertically with respect to the main surface of the semiconductor substrate.
In the conventional technique in fabricating vertical transistors, the nitride layer is employed as a barrier at least three times in a subsequent etching process and CMP (chemical mechanical polishing) process. Because of this, in order to secure an effective processing margin, the nitride layer should be formed at a thickness equal to or greater than about 1,500 Å. As a result, of this very thick nitride layer, the pillar structures including the nitride layer prone to leaning while undergoing any number of subsequent processes.
Conventional techniques in fabricating vertical transistors also suffer from voids being formed at conductive layers for the gate. That is it is difficult to completely fill in the spaces between the pillar structures with the conductive layers because of the presence of the neck parts. As a result, of conventionally forming a conductive layer for gates, voids can be produced in these spaces. Furthermore, when subsequently etching these conductive layers for gates, adjacent portions of the semiconductor substrate for gates are prone to being lost. As a result fabricating the vertical transistors with conventional techniques, the performance characteristics of the resultant semiconductor devices are likely to be degraded.